This application is based on and incorporates herein by reference Japanese Patent Application No. 2002-148090 filed on May 22, 2002 and No. 2003-133255 filed on May 12, 2003.
The present invention relates to a semiconductor device formed by filling a trench with an epitaxially grown film and to a method for manufacturing the device.
Such a semiconductor device is manufactured, for example, by: forming a trench defined by four sidewall surfaces, each of which is an Si{110} surface, or a surface of silicon on which a {110} plane is exposed, and a bottom surface, which is an Si(100) surface, or a surface of silicon on which a (100) plane is exposed, in an Si(100) surface of a silicon substrate; and depositing an epitaxially grown film to fill the trench. Specifically, the four sidewall surfaces defining the trench may be an Si(011) surface, an Si(0-1-1) surface, an Si(01-1) surface, and an Si(0-11) surface. The four surfaces of the sidewall surfaces are crystallographically equivalent to one another, but crystallographically differ from the bottom surface.
Alternatively, such a semiconductor device may also be manufactured by: forming a trench having four sidewall surfaces, each of which is an Si{111} surface, or a surface of silicon on which a {111} plane is exposed, and a bottom surface, which is an Si{110} surface, or a surface of silicon on which a {110} plane is exposed, in an Si{110} surface of a silicon substrate with an anisotropic wet etching using potassium hydroxide (KOH) aqueous solution; and depositing an epitaxially grown film to fill the trench, as disclosed in JP-A-2001-168327.
When a trench is formed with the anisotropic wet etching, the etch rate difference between the planes. Therefore, the plane orientations of the surfaces defining a trench are limited by the plane orientation of the surface of a substrate. As a result, each of the four sidewall surfaces and the bottom surface of the trench automatically become an Si{111} surface and an Si{110} surface, respectively.
The above technique for forming a trench can be applied to what is called a three-dimensional (3-D) structure MOSFET, which is disclosed in JP-A-2001-274398, and to a super junction MOSFET, which is disclosed in JP-A-2001-127289. In the 3-D structure MOSFET, a channel region has been formed such that a current mainly flows parallel to the surface of a substrate in the channel region, that is, the channel width direction, in which the width of the channel region is defined, is orthogonal to the surface of the substrate. The super junction MOSFET includes a p/n column layer.
Some 3-D structure MOSFETs and some super junction MOSFETs include a trench gate, which is a gate electrode formed on a sidewall surface of a trench with a gate oxide film therebetween. When a trench for a trench gate is formed, a trench defined by four sidewall surfaces, each of which is an Si{110} surface, and a bottom surface, which is an Si(100) surface, can be formed as well as the aforementioned trench filled with an epitaxially grown film if a silicon substrate having an Si(100) surface is used.
When a silicon substrate having an Si{110} surface is used, a trench for a trench gate can be formed using an anisotropic wet etching as well as the aforementioned trench filled with an epitaxially grown film, as disclosed in JP-A-2001-168327. In that case as well, the trench comes to have four sidewall surfaces, each of which is an Si{111} surface, and a bottom surface, which is an Si{110} surface.
A bar (-) should have been put above the corresponding numeral in order to show a crystallographic plane orientation. However, a bar is put before the corresponding numeral due to the restriction of notation in this specification. Braces { } means every crystallographically equivalent plane as in the ordinary notation system. For example, a {100} plane is any one of a (100) plane, a (010) plane, a (001) plane, a (-100) plane, a (0-10) plane, and a (00-1) plane.
In the semiconductor devices proposed in the above publications, there are three demands. The first demand is for suppressing the generation of crystallographic stress, or crystal defects, in an epitaxially grown film when the trench is filled with the epitaxially grown film. The generation of the crystal defects in the epitaxially grown film can be suppressed by removing the crystal defects existing in the surfaces defining the trench before the epitaxially grown film is formed. If crystal defects exist in the surfaces defining the trench, crystal defects are generated in the epitaxially grown film grown on the surfaces, too. Therefore, the generation of the crystal defects in the epitaxially grown film can be suppressed by removing the crystal defects existing in the surfaces defining the trench before the epitaxially grown film is formed.
Alternatively, the trench may be formed by wet etching, not by dry etching. Wet etching damages the surfaces defining the trench less than dry etching, so fewer crystal defects are generated in the surfaces defining the trench formed by wet etching. In addition, wet etching damages the silicon substrate less than dry etching, and wet etching generates fewer contamination layer, which is produced through the reaction. Therefore, the generation of the crystal defects in the epitaxially grown film can be more suppressed by forming the trench using wet etching than using dry etching.
The inventors of the present invention have conducted intensive studies on the cause of generating the crystal defects in order to obtain a method having the effect of suppressing the generation of crystal defects other than the aforementioned methods. The studies have shown that the difference in crystallographic plane between the bottom surface and the sidewall surfaces of the trench is one of the causes generating the crystal defects.
If the crystallographic plane exposed on the bottom surface of the trench differs from those on the sidewall surfaces of the trench, the growth rate of the epitaxially grown film becomes different between on the bottom surface and on the sidewall surfaces. Therefore, when the epitaxial grown film is formed, a stress is generated in the epitaxial grown film near the bottom corners of the trench. The stress causes the crystal defects.
The second demand is for increasing the breakdown voltage of the gate oxide film, on which the trench gate is formed. If a semiconductor device including a trench gate is manufactured by: forming a trench defined by four sidewall surfaces, each of which is an Si{110} surface, and a bottom surface, which is an Si(100) surface, in an Si(100) surface of a silicon substrate; and forming an gate oxide film on the four sidewall surfaces and the bottom surface by thermal oxidization, the gate oxide film becomes thinner on the bottom surface than on the sidewall surfaces. Therefore, the breakdown voltage of the gate oxide film is substantially determined by the thickness of the gate oxide film on the bottom surface. Thus, it is necessary to thicken the gate oxide film on the bottom surface in order to increase the breakdown voltage of the gate oxide film.
However, the semiconductor device is designed on the basis of the thickness of the gate oxide film on the sidewall surfaces because a channel region is formed in the sidewall surfaces. Therefore, it is difficult to thicken the gate oxide film only on the bottom surface without thickening the gate oxide film on the sidewall surfaces, if the trench is formed such that the above crystallographic planes are exposed on the sidewall surfaces and the bottom surface. From the standpoint of increasing the breakdown voltage of the gate oxide film, it is preferred that the thickness of the gate oxide film on the bottom surface be approximately equal to or thicker than those on the sidewall surfaces.
The third demand is for increasing the current flowing through the channel region without enlarging the chip size of a power device such as a 3-D structure MOSFET and a super junction MOSFET. The current flowing through the channel region is thought to be increased by increasing the cross-sectional area of the current passage. However, in that case, the chip sizes of the power devices becomes larger, so it is not preferable to increase the cross-sectional area of the current passage.
The present invention has been made in view of the above aspects. A first object of the present invention is to suppress the generation of crystal defects in an epitaxially grown film when a trench formed in a substrate is filled with the epitaxially grown film. A second object of the present invention is to increase the breakdown voltage of a gate oxide film in a semiconductor device including a trench gate. A third object of the present invention is to increase the current flowing through the channel region without enlarging the chip size of a power device such as a 3-D structure MOSFET and a super junction MOSFET.
To achieve the above objects, a semiconductor device according to the present invention includes a semiconductor substrate and a semiconductor layer. The semiconductor substrate has a main surface that is an Si{100} surface. The substrate has a trench in the main surface. The semiconductor layer is located on surfaces defining the trench to have common crystallographic planes with the semiconductor substrate. The trench is defined by a bottom surface, two long sidewall surfaces that face each other, and two short sidewall surfaces that face each other. The bottom surface and the long sidewall surfaces are Si{100} surfaces.